The present invention relates to a solid-state charge transfer device such as a charge coupled device (CCD).
A floating diffused region is widely used as a charge detecting means in a solid-state charge transfer device. In such a charge transfer device, a signal charge transferred through the channel region of a charge transfer section is led to the floating diffused region. After a quantity of charges transferred to the floating diffused region are converted into a voltage form signal to be outputted, the charges are drained to a reset drain through a channel under a reset gate.
The floating diffused region and the reset drain region are impurity-doped regions separately formed in a semiconductor substrate. The reset gate is provided on the semiconductor substrate between the floating diffused region and the reset drain region via an insulating layer. The floating diffused region, the reset gate electrode and the reset drain region constitute a field effect transistor (reset transistor).
The drain of charges from the floating diffused region is achieved by turning this reset transistor on. In order to accomplish this drain of charges, the potential of the reset drain should be higher than a certain level and held at that certain level. At the same time, the channel potential under the reset gate electrode in the aforementioned on-state of the reset transistor should be somewhat lower than that of the reset drain region. Because of these circumstances, the amplitude of the reset pulse to be applied to the reset gate electrode is usually greater than that of the transfer pulse of the charge transfer section. For instance, in an n-type buried channel charge coupled device, the amplitude of the transfer pulse is 5 volts; that of the reset pulse, 8 volts, and the voltage supplied to the reset drain region, 12 volts. Further in this example, when the reset pulse swings between 0 and 8 volts, the channel potential under the reset gate electrode changes between 7 volts and approximately 13.5 volts. As the channel potential (about 13.5 V) of a reset transistor in the on-state is higher than the drain voltage, which is 12 volts, the reset transistor is driven into an on-state in a complete transfer mode to reset the potential of the floating diffused region to that of the reset drain region.
In a system using an image sensor of a charge coupled device, such as a facsimile system, the power voltage for the peripheral circuits using the output from the charge coupled device is as low as 5 volts, for instance, so that a charge coupled device operable at a low power voltage is widely demanded.
The drain voltage of 12 volts can be realized with relative ease with a voltage booster. However, a voltage booster for enhancing the 5 volts of the reset pulse to 8 volts is more complex to provide than the aforementioned voltage booster from 5 volts to 15 volts and accordingly should be avoided in a semiconductor integrated circuit. On the other hand, if a reset pulse of 5 volts in amplitude is applied to the reset gate electrode, the channel potential of the reset transistor in on-state is about 11 volts in the above cited example, lower than the 12 volts in potential at the reset drain region. As a result, the reset transistor is driven into an on-state in an incomplete transfer mode. In such incomplete transfer mode operation, it is impossible to completely drain the signal charges from the floating diffused region, and the dynamic range of the signal output will become correspondingly narrower.
Japanese Patent laid-open Application No. 59-138376 discloses an output circuit for a charge coupled device operable with a low voltage supplied to the reset drain region. Two examples are disclosed therein. In the first example, first and second gates are arranged between the floating diffused region and the reset drain region. The first gate, similar to the charge transfer section, includes a pair of barrier and storage electrodes. The second gate is supplied with the same voltage as the output gate which is formed adjacent to the floating diffused region in the charge transfer section, but the insulating film formed thereunder is thickened to keep the channel potential thereunder lower than the channel potential under the output gate. The charges in the floating diffused region, after being transferred under the storage electrode of the first gate, are drained to the reset drain region. The first gate receives the same pulse as is supplied to the output gate. In this way, the voltage supplied to the reset drain region can be lowered, because the potential at the reset drain region is sufficient if having a value slightly deeper than the channel potential under the storage electrode of the first gate, when the channel potential is lower. The transfer from the floating diffused region to under the storage electrode of the first gate is performed in an incomplete transfer mode, because the channel potential under the first barrier electrode is lower than that under the storage electrode.
In the second example, a third gate and an intermediate drain are arranged between the floating diffused region and the first gate in the first example, and a large-capacity capacitor is connected between the intermediate drain and the grounding terminal. The charges in the floating diffused region, after being first drained into this intermediate drain through the third gate, are finally drained into the reset drain held at a constant voltage. The transfer of charges from the floating diffused region to the reset drain is performed in a complete transfer mode. By supplying a different pulse to the second gate from that applied to the output gate, the potential at the reset drain can be further lowered. A pulse of a greater amplitude is required, however, when the charge under the storage electrode of the first gate is drained into the reset drain.
The potential at the reset drain, in both the first and the second examples, is made lower than the channel potential under the storage electrode.
As the potential at the reset drain bears on the formation of a transfer channel in a buried channel type charge coupled device, it may become necessary not only to lower the voltage to be applied to the reset drain but also to alter the impurity concentration in the channel layer and the peak voltage of the transfer pulse. Therefore, it is not necessarily advantageous to keep the reset drain voltage low.